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description the CXD2443Q is a timing generator for the lcd panel lcx011 and lcx019 driver. this chip has a built-in serial interface circuit which allows various settings to be performed through external control from a microcomputer, etc. features generates the lcd panel lcx011/lcx019 drive pulse supports ntsc/pal (pal supported by scanning line conversion of video signal to 525h or pulse eliminate.) supports wide mode (when driving the lcx011) supports hd mode (when driving the lcx011) supports up/down and/or right/left inversion supports 3-panel projectors generates timing signal of external sample-and- hold circuit generates line inversion and field inversion signals ac drive of lcd panels during no signal line double-speed display realized with a built-in double-speed controller (ntsc/pal) (4:3 mode only) (line memory pd485505: nec) applications lcd projectors, etc. structure silicon cmos ic absolute maximum ratings (ta = 25?, v ss = 0v) supply voltage v dd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 4.5 to 5.5 v operating temperature topr ?0 to +75 ? ?1 CXD2443Q e96x31-ps timing generator for lcd panels sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic)
?2 CXD2443Q block diagram 16 : 9 4 : 3 hd master clock pwm1 pwm2 pwm3 peo1 peo2 peo3 hdr pll counter decoder phase comparator loop filter rpd1 rpd2 rpd3 fpd1 fpd2 fpd3 h-sync detector v-sync separator hsync vsync v-control counter v-position counter decoder & v-timing pulse generator pulse eliminator serial i/f h-sync detector phase comparator pll counter2 decoder clock2 loop filter direct clear field & line controller h-position counter decoder & h-timing pulse generator double scan converter test: 12, 20, 22, 23, 24, 25, 26, 27, 33, 60, 69 v dd : 3, 28, 53, 78 v ss : 4, 15, 29, 40, 54, 65, 79, 90 rck rstr wck rstw cki4 cko4 peo4 pwm4 rgt xrgt dwn xclr vst fldo vwa vwb sctr sclk sdat pre rpd4 fpd4 tc4 tc1 tc2 tc3 cksl cki5 cki3 cko3 cki2 cko2 cki1 cko1 5 10 11 83 88 89 99 98 97 91 92 2 6 9 16 17 18 19 21 30 34 82 84 76 77 87 96 93 13 14 32 44 45 70 71 72 73 80 1 74 75 81 7 8 39 38 37 36 35 31 41 42 43 46 47 48 49 50 51 52 55 56 57 58 59 68 67 63 64 66 61 62 86 85 10 0 95 94 hsta hck1a hck2a enb vck frp xfrp pcg1 xclp1 xclp2 pcg2 sh1a sh2a sh3a sh4a sh5a sh6a sh7a hstb hck1b hck2b sh1b sh2b sh3b sh4b sh5b sh6b sh7b
?3 CXD2443Q pin description pin no. symbol i/o description input pin for open status 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 xclr vwb v dd v ss tc1 fpd1 peo1 pwm1 rpd1 cko1 cki1 test2 hsync vsync v ss sctr sclk sdat pre test11 fldo test1 test3 test4 test5 test6 test7 v dd v ss vwa pcg1 dwn test8 vst vck i o i/o o i/o o o i/o i i i i i i i i o o o o o o system clear (low: all clear) v window pulse b output power supply gnd fpd1 output pulse width adjustment (ntsc/pal 4:3) phase comparator 1 output (ntsc/pal 4:3) loop filter integrator 1 output (ntsc/pal 4:3) loop filter integrator 1 input (ntsc/pal 4:3) phase comparator 1 output (ntsc/pal 4:3) oscillation cell 1 output (ntsc/pal 4:3) oscillation cell 1 input (ntsc/pal 4:3) test (not connected.) horizontal sync signal input (polarity set by serial data hpol.) vertical sync signal input (polarity set by serial data vpol.) gnd chip select input (serial transfer block) serial clock input (serial transfer block) serial data input (serial transfer block) preset setting (set to ntsc 4:3 mode when low.) test (not connected.) field discrimination signal output test (not connected.) test (not connected.) test (not connected.) test (not connected.) test (not connected.) test (connect to gnd.) power supply gnd v window pulse a output pcg1 pulse output (positive polarity) up/down inversion identification signal output (high: down, low: up) test (not connected.) v start pulse output (positive polarity) v clock pulse output h h
?4 CXD2443Q 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 enb hck2a hck1a hck2b v ss hck1b hstb hsta rgt xrgt pcg2 xclp1 xclp2 frp xfrp sh1a sh2a v dd v ss sh3a sh4a sh5a sh6a sh7a test9 sh1b sh2b sh3b sh4b v ss sh5b sh6b sh7b test10 rck o o o o o o o o o o o o o o o o o o o o o o o o o o o o o enb pulse output (negative polarity) h clock 2a pulse output h clock 1a pulse output h clock 2b pulse output gnd h clock 1b pulse output h start b pulse output (positive polarity) h start a pulse output (positive polarity) right/left inversion identification signal output (high: right, low: left) right/left inversion identification signal output (low: left, high: right) pcg2 pulse output (positive polarity) pedestal clamp pulse 1 output (negative polarity) pedestal clamp pulse 2 output (negative polarity) ac drive inversion timing output ac drive inversion timing output (reverse polarity of frp) sample-and-hold pulse 1a output (positive polarity) sample-and-hold pulse 2a output (positive polarity) power supply gnd sample-and-hold pulse 3a output (positive polarity) sample-and-hold pulse 4a output (positive polarity) sample-and-hold pulse 5a output (positive polarity) sample-and-hold pulse 6a output (positive polarity) sample-and-hold pulse 7a output (positive polarity) test (not connected.) sample-and-hold pulse 1b output (positive polarity) sample-and-hold pulse 2b output (positive polarity) sample-and-hold pulse 3b output (positive polarity) sample-and-hold pulse 4b output (positive polarity) gnd sample-and-hold pulse 5b output (positive polarity) sample-and-hold pulse 6b output (positive polarity) sample-and-hold pulse 7b output (positive polarity) test (not connected.) read clock output (for line buffer) pin no. symbol i/o description input pin for open status
?5 CXD2443Q * h: pull up, l: pull down 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 rstr wck rstw cko4 cki4 rpd4 fpd4 v dd v ss peo4 pwm4 tc4 tc2 fpd2 peo2 pwm2 rpd2 cko2 cki2 v ss cko3 cki3 rpd3 peo3 pwm3 fpd3 tc3 cksl cki5 hdr o o o i/o i o o i/o o i/o i/o o i/o o o i/o i i/o i o i/o o o i/o i i o read reset output (for line buffer, negative polarity) write clock output (for line buffer) write reset output (for line buffer, negative polarity) oscillation cell 4 output (line double-speed controller) oscillation cell 4 input (line double-speed controller) phase comparator 4 output (line double-speed controller) phase comparator 4 output (line double-speed controller) power supply gnd loop filter integrator 4 output (line double-speed controller) loop filter integrator 4 input (line double-speed controller) fpd4 output pulse width adjustment (line double-speed controller) fpd2 output pulse width adjustment (ntsc/pal 16:9) phase comparator 2 output (ntsc/pal 16:9) loop filter integrator 2 output (ntsc/pal 16:9) loop filter integrator 2 input (ntsc/pal 16:9) phase comparator 2 output (ntsc/pal 16:9) oscillation cell 2 output (ntsc/pal 16:9) oscillation cell 2 input (ntsc/pal 16:9) gnd oscillation cell 3 output (hd) oscillation cell 3 input (hd) phase comparator 3 output (hd) loop filter integrator 3 output (hd) loop filter integrator 3 input (hd) phase comparator 3 output (hd) fpd3 output pulse width adjustment (hd) pll system switching (high: built-in pll, low: external pll) external clock input (for external phase comparison) phase comparator output (for external phase comparison) h pin no. symbol i/o description input pin for open status
?6 CXD2443Q electrical characteristics 1. dc characteristics (v dd = 5.0 0.5v, v ss = 0v, topr = ?0 to +75?) item symbol min. typ. max. unit conditions supply voltage input, output voltages input voltage 1 input voltage 2 input voltage 3 output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 input leak current output leak current current consumption v dd v i, vo v ih v il vt + vt vt + ?vt vt + vt vt + ?vt v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol i i i il i i i oz i dd cmos input ttl schmitt trigger input cmos schmitt trigger input i oh = ?ma i ol = 4ma i oh = ?ma i ol = 8ma i oh = ?ma i ol = 6ma i oh = ?ma i ol = 3ma i oh = ?2ma i ol = 12ma * 4 * 6 * 8 * 10 * 12 4.5 vss 0.7v dd 2.2 0.8v dd v dd ?0.8 v dd ?0.8 v dd ?0.8 v dd /2 v dd /2 ?0 ?0 ?0 ?0 5.0 0.4 0.6 ?00 5.5 v dd 0.3v dd 0.8 0.2v dd 0.4 0.4 0.4 v dd /2 v dd /2 10 ?40 40 40 110 v v v v v v v v v v ? ? ma applicable pins * 1 hsync, sctr, vsync, sclk, sdat tc1, tc2, tc3, tc4 * 2 * 3 rck, wck peo1, peo2, peo3, peo4, cko4 cko1, cko2, cko3 * 5 * 7 * 9 * 11 at a 30pf load * 13 * 1 xclr, pre, cksl, cki1, cki2, cki3, cki4, cki5, cko1, cko2, cko3, cko4, pwm1, pwm2, pwm3, pwm4, peo1, peo2, peo3, peo4 * 2 hdr, enb, pcg1, pcg2, xclp1, xclp2, vst, frp, xfrp, vck, dwn, fldo, rgt, xrgt, vwa, vwb, rpd1, rpd2, rpd3, rpd4, fpd1, fpd2, fpd3, fpd4, tc1, tc2, tc3, tc4, rstr, rstw * 3 hsta, hck1a, hck2a, sh1a, sh2a, sh3a, sh4a, sh5a, sh6a, sh7a, hstb, hck1b, hck2b, sh1b, sh2b, sh3b, sh4b, sh5b, sh6b, sh7b * 4 normal input pins (v in = v ss or v dd ) * 5 hsync, vsync, sclk, sdat, sctr, cki5 * 6 pins with pull-up resistors (v in = v ss ) * 7 pre, xclr, cksl * 8 bidirectional pins (input status, v in = v ss or v dd ) * 9 cko1, cko2, cko3, cko4, peo1, peo2, peo3, peo4, tc1, tc2, tc3, tc4 * 10 at high impedance (v in = v ss or v dd ) * 11 rpd1, rpd2, rpd3, rpd4, fpd1, fpd2, fpd3, fpd4 * 12 fclk = 67mhz, v dd = 5.5v * 13 hsta, hstb, hck1a, hck2a, hck1b, hck2b, sh1a, sh2a, sh3a, sh4a, sh5a, sh6a, sh7a, sh1b, sh2b, sh3b, sh4b, sh5b, sh6b, sh7b, vck, enb, frp, pcg1, pcg2, xclp1, xclp2, rgt, dwn
?7 CXD2443Q 2. ac characteristics (v dd = 5.0 0.5v, vss = 0v, topr = ?0 to +75?) item min. typ. max. unit conditions clock input cycle output rise time output fall time cross-point time difference output rise delay time output fall delay time hck1 duty hck2 duty t r t f ? t t pr t pf t h /( t h + t l ) t l /( t h + t l ) cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf 21.3 16.0 15 28.2 15 ?0 48 48 20 20 10 15 15 52 52 ns symbol cki1 cki2 cki3 cki4 cki5 all outputs all outputs * 1 all outputs all outputs hck1a, hck1b hck2a, hck2b * 1 hck1a, 2a hck1b, 2b % applicable pins 3. serial transfer ac characteristics (v dd = 5.0 0.5v, vss = 0v, topr = ?0 to +75?) item min. typ. max. t s0 t s1 t h0 t h1 t w1l t w1h t w2 t w3 sctr setup time, activated by rise of sclk sdat setup time, activated by rise of sclk sctr hold time, activated by rise of sclk sdat hold time, activated by rise of sclk sclk pulse width sclk pulse width 4t 2t 4t 2t 2t 2t 5t 5t unit ns symbol t: master clock cycle (ns)
?8 CXD2443Q 100% 90% 90% 10% 10% tr tf tpf v dd 0v v dd 0v v dd 0v output output cki1, cki2 cki3, cki4 tpr hck1a hck1b hck2a hck2b 50% 50% v dd 0v v dd 0v 50% 50% d t d t 50% 50% 50% t l t h hck1a hck1b note) hck2 is the reverse phase of hck1. 4. timing definitions ac characteristics serial transfer ac characteristics sctr 50% 50% 50% sclk sdat ts0 tw1l tw1h ts1 th1 ts1 th1 tw2 d14 d9 d7 50% d15 50% th0 tw3 note) see "serial transfer timing" on p. 17 for the timing relationship between d15 to d0 and each pulse. d15 d8 d0
?9 CXD2443Q lcx011 dot arrangement (1) (4:3 display) the dot arrangement is a delta arrangement. also, the shaded region in the diagram is not displayed. r1 corresponds to sig2, g1 to sig1, b1 to sig3, r2 to sig5, g2 to sig4 and b2 to sig6. pc pcx v dd v ss wd wdx jtn jtp a r1 aa g1 a b1 aa r2 a g2 a b2 aa aa g1 a a b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 aa r2 a g2 a b2 aa aa g1 a a b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 aa r2 a g2 a b2 aa a a aa a aa a aa a aa a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a a a aa aa a a aa aa a aa a aa a a aa aa a a a a aa aa a a aa aa a aa a aa a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dl1 sid aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a aa a aa a aa a aa a a aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa a aa a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a a a aa aa a a aa aa a a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dl2 a r1 aa g1 a b1 a r2 a g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 a r2 a g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 a r2 a g2 a b2 a aa a aa a aa a aa a a aa a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa a a aa aa a a a a aa aa a a a aa a aa a aa a aa a a a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a aa aa a aa a a a a a a aa aa a a aa aa a a aa aa a aa a a a a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 1 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a aa a aa a aa a aa aa a aa a a aa a aa a aa aa a a aa aa aa aa a a aa aa a a aa a aa a aa aa a a aa aa aa aa a a aa aa a a aa a aa a aa a aa a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a a a aa aa a a aa aa a a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a aa a aa a aa aa a a aa aa aa aa a a aa aa a a aa a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a aa a aa a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 34 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 a a r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 a a r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa a aa a a a aa a a aa a aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a aa aa a a a a a a aa a a aa a aa aa aa a a aa aa a a a a a a aa a a aa a aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw ? ? ? a r1 a g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 a g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 a g1 a b1 a r2 aa g2 a b2 a aa a aa a a a a aa a aa a a aa a aa a a a a a a aa aa a a aa aa a a a aa a aa a a a a a a aa aa a a aa aa a a a aa a aa a a a a a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a a a a aa a a a aa aa a a aa aa a a a a a a a a aa a a aa a aa a a a a a a aa aa a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 234 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 aa aa r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 aa aa r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa a aa a a aa aa a a aa a aa aa a aa a a aa aa aa a a a a aa aa a a aa aa aa a aa a a aa aa aa a a a a aa aa a a aa aa aa a aa a a aa aa a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a aa aa a a a a aa aa aa a a aa a aa aa aa a a aa aa a a a a aa aa aa a a aa a aa aa a aa a a aa aa aa a a a a aa aa a a aa aa aa a aa a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw ? ? ? a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a aa a aa a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 267 a r1 a g1 aa b1 a a g1 aa aa b1 a a r1 a r1 a g1 aa b1 a a g1 aa aa b1 a a r1 a r1 a g1 aa b1 a aa a a a aa a aa a a a a a aa aa a aa a a a a a aa aa a aa a a a aa g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 a a aa aa a a a a aa a a aa aa a a a a aa a aa a a a a a aa aa a aa a g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 aa r1 a g1 a b1 a r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 a b1 a r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 a b1 a r2 a g2 aa b2 aa a aa a aa a aa a a aa a aa a a aa a aa a aa aa a a a a aa aa a a aa aa a a aa a aa a aa aa a a a a aa aa a a aa aa aa a aa a aa a aa a a a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a aa aa a a aa aa a a aa a a a a aa aa aa a a aa aa a a aa aa a a aa a a a a aa a a aa a aa a aa aa a a a a aa aa a a aa aa a a aa a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dr1 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a aa a aa a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dr2 1 2 3 4 479 480 2 dots 2 dots 480 dots (effective 31.6701mm) ? ? ? ? ? ? ? ? ? odd = 13 dots even = 13 dots odd = 200 dots even = 200 dots odd = 1200 dots even = 1199 dots (effective 23.7501mm) odd = 200 dots even = 200 dots odd = 13 dots even = 14 dots odd = 1626 dots even = 1626 dots
?10 CXD2443Q lcx011 dot arrangement (2) (16:9 display) the dot arrangement is a delta arrangement. also, the shaded region in the diagram is not displayed. r1 corresponds to sig2, g1 to sig1, b1 to sig3, r2 to sig5, g2 to sig4 and b2 to sig6. pc pcx v dd v ss wd wdx jtn jtp a r1 aa g1 a b1 aa r2 a g2 a b2 aa aa g1 a a b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 aa r2 a g2 a b2 aa aa g1 a a b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 aa r2 a g2 a b2 aa a a aa a aa a aa a aa a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a a a aa aa a a aa aa a aa a aa a a aa aa a a a a aa aa a a aa aa a aa a aa a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dl1 sid aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a aa a aa a aa a aa a a aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa a aa a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a a a aa aa a a aa aa a a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dl2 a r1 aa g1 a b1 a r2 a g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 a r2 a g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 aa aa r2 a r1 aa g1 a b1 a r2 a g2 a b2 a aa a aa a aa a aa a a aa a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa a a aa aa a a a a aa aa a a a aa a aa a aa a aa a a a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a aa aa a aa a a a a a a aa aa a a aa aa a a aa aa a aa a a a a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 1 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 aa b1 a r2 a g2 aa b2 a a aa a aa a aa a aa aa a aa a a aa a aa a aa aa a a aa aa aa aa a a aa aa a a aa a aa a aa aa a a aa aa aa aa a a aa aa a a aa a aa a aa a aa a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a a a aa aa a a aa aa a a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a aa a aa a aa aa a a aa aa aa aa a a aa aa a a aa a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a aa a aa a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 34 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 a a r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 a a r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa a aa a a a aa a a aa a aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a aa aa a a a a a a aa a a aa a aa aa aa a a aa aa a a a a a a aa a a aa a aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw ? ? ? a r1 a g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 a g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 a g1 a b1 a r2 aa g2 a b2 a aa a aa a a a a aa a aa a a aa a aa a a a a a a aa aa a a aa aa a a a aa a aa a a a a a a aa aa a a aa aa a a a aa a aa a a a a a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a a a a aa a a a aa aa a a aa aa a a a a a a a a aa a a aa a aa a a a a a a aa aa a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 234 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 aa aa r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 a a b2 aa aa r2 aa r1 a g1 a b1 aa r2 a g2 aa b2 aa a aa a a aa aa a a aa a aa aa a aa a a aa aa aa a a a a aa aa a a aa aa aa a aa a a aa aa aa a a a a aa aa a a aa aa aa a aa a a aa aa a a aa a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a aa aa a a a a aa aa aa a a aa a aa aa aa a a aa aa a a a a aa aa aa a a aa a aa aa a aa a a aa aa aa a a a a aa aa a a aa aa aa a aa a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw ? ? ? a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a aa a aa a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw 267 a r1 a g1 aa b1 a a g1 aa aa b1 a a r1 a r1 a g1 aa b1 a a g1 aa aa b1 a a r1 a r1 a g1 aa b1 a aa a a a aa a aa a a a a a aa aa a aa a a a a a aa aa a aa a a a aa g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 a a aa aa a a a a aa a a aa aa a a a a aa a aa a a a a a aa aa a aa a g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 r1 g1 b1 g1 b1 r1 aa r1 a g1 a b1 a r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 a b1 a r2 a g2 aa b2 aa aa g1 a a b1 aa aa r1 a a g2 aa aa b2 a a r2 aa r1 a g1 a b1 a r2 a g2 aa b2 aa a aa a aa a aa a a aa a aa a a aa a aa a aa aa a a a a aa aa a a aa aa a a aa a aa a aa aa a a a a aa aa a a aa aa aa a aa a aa a aa a a a a aa g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 aa aa a a aa aa a a aa aa a a aa a a a a aa aa aa a a aa aa a a aa aa a a aa a a a a aa a a aa a aa a aa aa a a a a aa aa a a aa aa a a aa a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dr1 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a a g1 aa aa b1 a a r1 aa aa g2 a a b2 a a r2 a r1 aa g1 a b1 a r2 aa g2 a b2 a aa a aa a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 r1 g1 b1 r2 g2 b2 g1 b1 r1 g2 b2 r2 gate sw dr2 1 2 3 4 479 480 2 dots 2 dots 480 dots (effective 31.6701mm) ? ? ? ? ? ? ? ? ? odd = 13 dots even = 13 dots odd = 1600 dots even = 1599 dots (effective 31.6701mm) odd = 13 dots even = 14 dots odd = 1626 dots even = 1626 dots
?11 CXD2443Q lcx019 dot arrangement the dot arrangement is a delta arrangement. also, the shaded region in the diagram is not displayed. r1 corresponds to sig2, g1 to sig1, b1 to sig3, r2 to sig5, g2 to sig4 and b2 to sig6. pc pcx a a aa aa a a aa aa a a a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a aa a aa a a aa aa a a a a aa aa a a aa aa a aa a aa a a aa aa a a a a aa aa a a aa aa a aa a aa a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a a aa aa a a aa aa a a a a aa a a aa a aa a aa a aa a a aa a a aa a aa a aa a aa a a aa aa a a a a aa aa a a aa aa a aa a aa a a aa aa a a aa aa a aa aa gate sw dr1 psig aa aa a a aa aa a a a a aa aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa aa a a aa aa a a a a aa aa a a aa a aa a aa a aa a a aa a a aa a aa a aa a aa a a aa a a a a aa aa a a aa aa a a aa a aa a a aa a a aa aa a aa aa a gate sw dr2 a a aa aa a a a a aa aa a a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa a aa a a a a a a aa aa a a aa aa a a aa aa a aa a a a a a a aa aa a a aa aa a a aa aa a aa a a a a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa a a aa aa a a a a aa aa a a a a a aa a aa a aa a a a a a aa a aa a aa a aa a a a a a a aa aa a a aa aa a a aa aa a aa a a a a a aa aa a aa aa a aa aa gate sw 1 aa aa a a a a a a a a aa aa a a aa a aa a aa aa a a a a a a a a aa aa a a aa a aa a aa a a a a aa a a a a aa aa a a aa aa a a aa a a a a aa a a a a aa aa a a aa aa a a aa a a a a aa a a aa a aa a aa aa a a a a a a a a aa aa a a aa a aa a aa aa a a a a a a a a aa aa a a aa a aa a aa a a a a aa a a aa a aa a aa a a a a aa a a a a aa aa a a aa aa a a aa a a a a aa a a aa aa a aa aa a gate sw a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a a aa aa a a a a aa aa a a a aa a aa a a a aa a a aa a a aa a aa a a a aa a a aa a a a aa aa a a aa aa a a a a a aa a a aa a a aa aa a aa aa a a gate sw 201 aa aa a a a a aa aa a a aa aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa a a aa a aa aa aa a a aa aa a a a a aa aa aa a a aa a aa aa aa a a aa aa a a a a aa aa aa a a aa a aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa aa a a a a aa aa a a aa aa aa a aa a a a aa a a aa a aa aa a aa a a aa aa a a aa a aa aa aa a a aa aa a a a a aa aa aa a a aa a aa aa aa a aa aa a a a aa aa gate sw dl2 a a a a aa aa a a aa aa a a a aa a aa a a a a a aa aa a a aa aa a a a aa a aa a a a a a aa a a a aa aa a a aa aa a a a a a a aa a a a aa aa a a aa aa a a a a a a aa a a aa a aa a a a a a aa aa a a aa aa a a a aa a aa a a a a a aa aa a a aa aa a a a aa a aa a a a a a aa a a aa a aa a a a a a aa a a a aa aa a a aa aa a a a a a a aa a a aa aa a aa aa a gate sw dr1 1 2 3 4 479 480 odd = 1200 dots even = 1199 dots a r a r a a r a a r a r a r a r a r a a r a r 2 dots gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgb rgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgb rgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgb rgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb gb rgbrgbrgbrgb rgbrgbrgbrgb rgb r rgb r rgb r rgb r rgb r rgb r rgb r rgb r rgb r rgb r gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb gb rgbrgbrgbrgb rgbrgbrgb rgb r r r r r r r r r gb rgbrgbrgbrgb rgbrgbrgb rgb r 480 dots 2 dots
?12 CXD2443Q (4) pal (csync input) sync signal phase reference odd field even field csync csync (5) hd sync signal phase reference sync signal phase reference odd field even field hsync vsync hsync vsync input signal protocol 1. horizontal sync signal a double-speed hsync or standard hsync (or csync) should be input for ntsc and pal display modes. double-speed hsync and standard hsync input switching is set by the serial data (snsl). note) the double-speed hsync should have a cycle and width 1/2 that of the standard hsync. the signal obtained by cutting off only the bottom of the ternary sync should be input for hd display mode. the input sync signal polarity is not fixed, and is set by the serial data (hpol). when using the built-in line double-speed controller, set serial data snsl to low. the built-in line double- speed controller supports only the standard hsync (or csync). 2. vertical sync signal a normal-speed vsync (or csync) should be input for ntsc and pal display modes. a vsync that has been sync separated by sync sep. should be input for hd display mode. the input sync signal polarity is not fixed, and is set by the serial data (vpol). the phase relationship between hsync and vsync is specified as follows for the CXD2443Q. (1) double-speed ntsc (2) double-speed pal (3) ntsc (csync input) sync signal phase reference vsync double-speed hsync sync signal phase reference vsync double-speed hsync sync signal phase reference odd field even field csync csync
?13 CXD2443Q description of operation clock input the CXD2443Q supports two types of pll circuits. pll switching is performed by cksl (pin 98). (high: built-in pll, low: external pll) note) the built-in line double-speed controller pll is supported only by the built-in pll. (1) built-in pll (cki1, cki2, cki3, cki4) a pll circuit is comprised by the built-in phase comparator and an external vco circuit. there are four clock inputs which support the following modes. cki1: ntsc/pal 4:3 cki2: ntsc/pal 16:9 cki3: hd cki4: for built-in line double-speed controller the pll lock for this system is adjusted by setting the rpd and fpd transition points so that they fall at the center of the windows as shown in the diagram below. (see the application circuit.) (2) external pll (cki5) the cki5 pin is the clock input pin when using an external pll ic. the 1/n frequency divider output is output from the hdr pin (frequency division ratio n/2) for the pll ic. set cksl (pin 98) to low to switch to the external pll. ac driving of lcd panels for no signal the following measures have been adopted to allow ac driving of lcd panels even when there is no signal. horizontal direction pulse the pll is set to free running status. the frequency of the horizontal direction pulse at this time is dependent on the pll free running frequency. vertical direction pulse the number of lines is counted by an internal counter and the vertical direction pulses (vst, frp) are output at a specified cycle. for the CXD2443Q, no signal (free running) status is judged if there is no vsync input for longer than the following (free running detection) periods. aa bb 800ns output waveform during pll lock hsync rpd fpd hsync hdr n f h n/2 f h mode ntsc pal hd v cycle for no signal 544h (272h) 640h (320h) 576h free running detection 1024h (512h) note) numbers in parentheses are for when using the built-in line double-speed controller.
?14 CXD2443Q right/left and/or up/down inversion in delta arrangement lcd panels, the same signal lines are separated by 1.5 dots for each horizontal line. therefore, a 1.5 dot offset is added between lines to the lcd's horizontal direction start pulses hst and hck and sample-and-hold pulse (sh). when driving an lcd panel with right and left inversed, the dot arrangement is asymmetrical so an offset is attached to hst, hck and sh. when driving with up and down inversed, the relationship between the panel's odd and even line offsets is reversed. right scan left scan down scan up scan h scanner v scanner effective display area 1.5f h right and down scan, even line right and up scan, odd line 1.5f h down scan, odd line up scan, even line left and down scan, even line left and up scan, odd line mck hst
?15 CXD2443Q when using three lcd panels b outputs (hstb, hck1b, hck2b, sh1b to 7b) are provided for driving three lcd panels with and without right/left inversion at the same time. these b outputs are the right/left inversed timings of the a outputs (hsta, hck1a, hck2a, sh1a to 7a). xrgt (rgt inversed output) is also provided for right/left inversion scanning. application circuit (driving three lcd panels) 36 35 34 31 32 39 38 37 41 42 43 44 45 51 52 55 56 57 58 59 68 67 63 64 66 61 62 right scan (a outputs) tg note) all three panels face the same direction. left scan (b outputs) common panel 1 (right scan) panel 2 (right scan) panel 3 (left scan) signal driver signal driver signal driver sh1a sh2a sh3a sh4a sh5a sh6a sh7a hsta hck1a hck2a rgt sh1b sh2b sh3b sh4b sh5b sh6b sh7b hstb hck1b hck2b xrgt dwn enb vck pcg1 or pcg2 vst 46
?16 CXD2443Q built-in line double-speed controller this controller is designed to use the pd485505 (nec/high-speed line buffer) as the system line memory ic, and generates the double-speed processing pulses rstw (reset write), wck (write clock), rstr (reset read) and rck (read clock). operation is as follows. write operation is started at the rstw timing, and this memory information is read twice at double speed at the rstr timing which is delayed by 1/2h and 1h from the rstw timing. the write and read clock frequencies at this time are generated by the built-in pll (cki4). see the specifications for a detailed description of pd485505 operation. adc dac line mem. pd485505 CXD2443Q rstr rck rstw wck r, g, b in hsync vsync csync mck : f double-speed display system block hsync rstw wck rstr rck f/2 f hsync rstw rstr double-speed display timing note) see the timing charts for details.
?17 CXD2443Q xclr pin the CXD2443Q should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. serial transfer operation 1. control method the CXD2443Q operation timing is controlled by serial data. the control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise of sclk. this fetching operation starts from the fall of sctr and is completed at the next rise of sctr. serial transfer timing 2. control data when using the CXD2443Q, set the control data corresponding to each signal source according to the formats in the table below. d15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 hp8 vm7j vm7k hp7 vm6j vm6k hp6 vm5j vm5k test4 hp5 vm4j vm4k test3 hp4 vp4 slsh4 vm3j vm3k sl3b snsl hp3 vp3 slsh3 vm2j vm2k vpol xhd hp2 vp2 slsh2 cp2 pcgw2 vm9j vm1j vm9k vm1k test1 ma dwn hpol slvwb xwid hp1 vp1 slsh1 cp1 pcgw1 vm8j vm0j vm8k vm0k slba test2 rgt slfr sleg nt-pal (a) h-position (b) v-position (c) sh-position (d) xclp-position (e) pcg-position (f) vwa-position (vwa pulse) (g) double-speed setting (h) double-speed pal pulse eliminate (i) right/left and/or up/down inversion (j) various settings (k) mode settings d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 note) 1. set "high" as the test1, test2, test3 and test4 data. 2. "? indicates not set. address data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdat sclk sctr address data function
?18 CXD2443Q serial settings during power on the CXD2443Q should be forcibly reset during power on using the xclr pin. after being forcibly reset, the master clock for the CXD2443Q is supplied from cki3. the initial serial data after power on is loaded to the CXD2443Q using the clock from cki3. serial settings during pll free running when the pll is in free running status, the serial clock cycle (f ns) may be less than f 3 2t with respect to the master clock cycle (t ns). take care that the serial clock cycle setting is such that f 3 2t during pll free running. each control data is described in detail below. (a) h-position (hp1, hp2, hp3, hp4, hp5, hp6, hp7, hp8) these bits set the horizontal display start position. the minimum adjustment width is 1 dot, and adjustment of up to 128 dots is possible with respect to the design center value. (data: 8 bits) design center value hp1 hp2 hp3 hp4 hp5 hp6 hp7 hp8 lllllllh mode variable time (128f h ) ntsc (4:3) ntsc (16:9) pal (4:3) pal (16:9) hd 2.8s 2.1s 2.7s 2.0s 1.9s (b) v-position (vp1, vp2, vp3, vp4) these bits set the vertical display start position. the minimum adjustment width is 1h, and adjustment of up to 8h is possible with respect to the design center value. (data: 4 bits) design center value vp1 vp2 vp3 vp4 lllh
?19 CXD2443Q (c) sh-position (slsh1, slsh2, slsh3, slsh4) these bits control the phase relationship between hck1, hck2 and sh1, 2, 3, 4, 5, 6 and 7. the minimum adjustment width is 0.5 dots, and adjustment of up to 6 dots is possible. (data: 4 bits) hckn sh1 sh2 sh3 sh4 sh5 sh6 sh7 slsh1, 2, 3, 4 llll (0) hlll (1) lhll (2) hhll (3) llhl (4) hlhl (5) lhhl (6) hckn sh1 sh2 sh3 sh4 sh5 sh6 sh7 rgt = high: a output rgt = low: b output rgt = low: a output rgt = high: b output
?20 CXD2443Q hckn sh1 sh2 sh3 sh4 sh5 sh6 sh7 slsh1, 2, 3, 4 hhhl (7) lllh (8) hllh (9) lhlh (a) hhlh (b) ** hh (c, d, e, f) hckn sh1 sh2 sh3 sh4 sh5 sh6 sh7 rgt = high: a output rgt = low: b output rgt = low: a output rgt = high: b output
?21 CXD2443Q (d) xclp-position (cp1, cp2) these bits control the phase relationship between pedestal clamp pulses xclp1 and xclp2 and hsync. the phase can be adjusted in 400ns units to four levels. (data: 2 bits) xclp1 cp1 = h, cp2 = h cp1 = l, cp2 = h (design center value) cp1 = h, cp2 = l cp1 = l, cp2 = l xclp2 cp1 = h, cp2 = h cp1 = l, cp2 = h (design center value) cp1 = h, cp2 = l cp1 = l, cp2 = l ?50ns ?50ns 0 150ns 950ns 1750ns 2550ns 550ns 1350ns 2150ns hsync 1.2s 1.4s 1.6s 1.8s ll hl lh pcgw1, 2 = hh fixed pcg pulse (e) pcg-position (pcgw1, pcgw2) these bits control the pcg1 pulse width (falling edge). the width can be adjusted in 200ns units to four levels. (data: 2 bits)
?22 CXD2443Q (f) vwa-position (vm0j, vm1j, vm2j, vm3j, vm4j, vm5j, vm6j, vm7j, vm8j, vm9j, vm0k, vm1k, vm2k, vm3k, vm4k, vm5k, vm6k, vm7k, vm8k, vm9k) the vwa pulse rise and fall can be varied in 1h units in the vertical direction. rise position: vw0j to 9j (10 bits) fall position: vw0k to 9k (10 bits) rise, fall transition points: enb pulse fall position reference (0): 1.5h before the vst output position reference (0) vst double-speed hsync (g) double-speed setting (slba) this bit sets the built-in line double-speed controller. slba high: line double-speed controller off low: line double-speed controller on the loop counter is an n multiple of the following. ntsc pal 910f h 1135f h notes on operation the built-in line double-speed controller is supported only when driving a single lcd panel in ntsc/pal 4:3 mode. when using the CXD2443Q in other modes (ntsc/pal 16:9 mode, hd mode, 3-panel mode), be sure to set the line double-speed controller to off (slba = high).
?23 CXD2443Q (h) double-speed pal pulse eliminate (ma) this bit sets the double-speed pal pulse eliminate (conversion from 575 to 480 vertical lines by 6, 7 pulse eliminate). the setting is as follows. ma high: pulse eliminate off low: pulse eliminate on the 2n + 1 field pulse eliminate position is shifted 1h (line) to the rear with respect to the 2n field pulse eliminate position. (i) right/left and/or up/down inversion (rgt, dwn) these bits switch the right/left inversion and/or up/down inversion timing for the lcd panel. note) the b outputs (hstb, hcknb, shnb) are the outputs for 3-panel projectors, and are output at the right/left inversed timing of the a outputs. (j) various settings slfr this bit sets the cycle of the lcd ac drive signals frp and xfrp. high: 1h (line) inversion low: 1f (field) inversion vpol, hpol these bits set the input sync polarity. high: negative polarity low: positive polarity setting rgt dwn h h l l h l h l rgt xrgt l h l h h l h l output right scan, down scan left scan, down scan right scan, up scan left scan, up scan a outputs left scan, down scan right scan, down scan left scan, up scan right scan, up scan b outputs dwn h h l l
?24 CXD2443Q sl3b this bit sets the 3-panel projector output (b outputs) switching. the hstb, hcknb, and shnb outputs can be switched on and off. high: b outputs off low: b outputs on note) when driving a single lcd panel, set the b outputs to off (sl3b = high). slvwb this bit sets the vwb output. high: vwb off low: vwb on sleg this bit sets the vwb transition timing. high: hsync front edge low: hsync rear edge note) vwb is the equalizing pulse masking pulse. the rise position is counted from the vd inside the previous field. therefore, when the number of lines within one field differs from the standard protocol, the phase between the next field's vsync and the vwb rise position changes. the phase also changes when a value other than the default value is used as the v-position setting. (k) mode settings snsl this bit sets the double-speed hsync and standard hsync (or csync) input switching. high: double-speed hsync input low: standard hsync (csync) input note) when using the built-in line double-speed controller, only the standard hsync is supported. set snsl to standard hsync input (snsl = low). nt-pal, xwid, hd these bits set the various display modes. nt-pal xwid xhd ntsc (4:3) h h h ntsc (16:9) h l h pal (4:3) l h h pal (16:9) l l h hd ** l note) test mode serial data test1, test2, test3 and test4 are test mode data. care should be taken as these bits are not used, and must be set to high.
?25 CXD2443Q note) the frp polarity is not specified for each line and field. odd line 1444 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (18f h ) 1.2s (55f h ) 0.3s (14f h ) 1.8s (83f h ) 2.1s (97f h ) 1.0s (46f h ) 2.0s (92f h ) 1.2s (55f h ) 0.55s (26f h ) 0.15s (7f h ) 4.38s (202f h ) 12f h 2.35s (108f h ) 6f h ntsc (4:3) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: h xwid: h xhd: h loop counter 1464f h master clock 46.07mhz
?26 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1444 odd line 2.35s (108f h ) 4.38s (202f h ) 4.38s (202f h ) 12f h 12f h 6f h sh6b sh7b ntsc (4:3) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: h xwid: h xhd: h loop counter 1464f h master clock 46.07mhz
?27 CXD2443Q note) the frp polarity is not specified for each line and field. even line 1444 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (18f h ) 1.16s (53.5f h ) 0.3s (14f h ) 1.8s (83f h ) 2.1s (97f h ) 1.0s (46f h ) 2.0s (92f h ) 1.2s (55f h ) 0.55s (26f h ) 0.15s (7f h ) 4.35s (200.5f h ) 12f h 2.35s (108f h ) 6f h ntsc (4:3) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: h xwid: h xhd: h loop counter 1464f h master clock 46.07mhz
?28 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1444 even line 2.35s (108f h ) 12f h 12f h 6f h sh6b sh7b 4.35s (200.5f h ) 4.42s (203.5f h ) ntsc (4:3) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: h xwid: h xhd: h loop counter 1464f h master clock 46.07mhz
?29 CXD2443Q note) the frp polarity is not specified for each line and field. odd line 1480 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (19f h ) 1.2s (57f h ) 0.3s (14f h ) 1.8s (84f h ) 2.1s (98f h ) 1.0s (47f h ) 2.0s (93f h ) 1.2s (57f h ) 0.55s (25f h ) 0.15s (7f h ) 4.99s (234f h ) 2.35s (110f h ) 6f h 12f h pal (4:3) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: l xwid: h xhd: h loop counter 1500f h master clock 46.88mhz
?30 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1480 odd line 2.35s (110f h ) 6f h sh6b sh7b 4.99s (234f h ) 4.99s (234f h ) 12f h 12f h pal (4:3) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: l xwid: h xhd: h loop counter 1500f h master clock 46.88mhz
?31 CXD2443Q note) the frp polarity is not specified for each line and field. even line 1480 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (19f h ) 1.18s (55.5f h ) 0.3s (14f h ) 1.8s (84f h ) 2.1s (98f h ) 1.0s (47f h ) 2.0s (93f h ) 1.2s (57f h ) 0.55s (25f h ) 0.15s (7f h ) 4.96s (232.5f h ) 2.35s (110f h ) 6f h 12f h pal (4:3) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: l xwid: h xhd: h loop counter 1500f h master clock 46.88mhz
?32 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1480 even line 2.35s (110f h ) 6f h 4.96s (232.5f h ) 5.02s (235.5f h ) 12f h 12f h sh6b sh7b pal (4:3) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: l xwid: h xhd: h loop counter 1500f h master clock 46.88mhz
?33 CXD2443Q note) the frp polarity is not specified for each line and field. odd line 1932 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (25f h ) 1.2s (74f h ) 0.3s (18f h ) 1.8s (111f h ) 2.1s (129f h ) 1.0s (61f h ) 2.0s (123f h ) 1.2s (74f h ) 0.55s (34f h ) 0.15s (9f h ) 6f h 2.35s (144f h ) 4.54s (279f h ) 12f h ntsc (16:9) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: h xwid: l xhd: h loop counter 1952f h master clock 61.43mhz
?34 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1932 odd line 12f h 6f h 12f h 2.35s (144f h ) 4.54s (279f h ) 4.54s (279f h ) sh6b sh7b ntsc (16:9) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: h xwid: l xhd: h loop counter 1952f h master clock 61.43mhz
?35 CXD2443Q note) the frp polarity is not specified for each line and field. even line 1932 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (25f h ) 1.18s (72.5f h ) 0.3s (18f h ) 1.8s (111f h ) 2.1s (129f h ) 1.0s (61f h ) 2.0s (123f h ) 1.2s (74f h ) 0.55s (34f h ) 0.15s (9f h ) 4.52s (277.5f h ) 2.35s (144f h ) 6f h 12f h ntsc (16:9) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: h xwid: l xhd: h loop counter 1952f h master clock 61.43mhz
?36 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1932 even line 12f h 6f h sh6b sh7b 2.35s (144f h ) 4.52s (277.5f h ) 4.57s (280.5f h ) 12f h ntsc (16:9) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: h xwid: l xhd: h loop counter 1952f h master clock 61.43mhz
?37 CXD2443Q note) the frp polarity is not specified for each line and field. odd line 1980 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (25f h ) 1.2s (75f h ) 0.3s (19f h ) 2.1s (131f h ) 1.0s (63f h ) 2.0s (125f h ) 1.2s (75f h ) 0.55s (35f h ) 0.15s (10f h ) 5.17s (323f h ) 12f h 2.35s (147f h ) 6f h 1.8s (112f h ) pal (16:9) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: l xwid: l xhd: h loop counter 2000f h master clock 62.5mhz
?38 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1980 odd line 12f h 12f h 2.35s (147f h ) 5.17s (323f h ) 5.17s (323f h ) 6f h sh6b sh7b pal (16:9) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: l xwid: l xhd: h loop counter 2000f h master clock 62.5mhz
?39 CXD2443Q note) the frp polarity is not specified for each line and field. even line 1980 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (25f h ) 1.18s (73.5f h ) 0.3s (19f h ) 1.8s (112f h ) 2.1s (131f h ) 1.0s (63f h ) 2.0s (125f h ) 1.2s (75f h ) 0.55s (35f h ) 0.15s (10f h ) 5.14s (321.5f h ) 12f h 2.35s (147f h ) 6f h pal (16:9) horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h snsl: h nt-pl: l xwid: l xhd: h loop counter 2000f h master clock 62.5mhz
?40 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1980 even line 12f h 12f h 6f h 2.35s (147f h ) 5.14s (321.5f h ) 5.19s (324.5f h ) sh6b sh7b pal (16:9) horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l snsl: h nt-pl: l xwid: l xhd: h loop counter 2000f h master clock 62.5mhz
?41 CXD2443Q note) the frp polarity is not specified for each line and field. odd line 1916 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (26f h ) 1.2s (80f h ) 0.3s (20f h ) 1.8s (120f h ) 2.1s (140f h ) 1.0s (67f h ) 2.0s (133f h ) 1.2s (80f h ) 0.55s (36f h ) 0.15s (9f h ) 3.84s (256f h ) 6f h 0.59s (40f h ) 12f h 1936 1956 hd horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h xhd: l loop counter 1976f h master clock 66.69mhz
?42 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 340 60 20 320 300 280 260 240 220 200 180 160 140 120 100 80 40 0 1956 1936 1916 odd line 6f h 12f h 12f h 3.84s (256f h ) 3.84s (256f h ) 0.59s (40f h ) sh6b sh7b hd horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l xhd: l loop counter 1976f h master clock 66.69mhz
?43 CXD2443Q 6f h note) the frp polarity is not specified for each line and field. even line 1916 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 mck hsync xclp1 xclp2 hsta hck1a hck2a sh1a sh2a sh3a sh4a sh5a sh6a sh7a enb vck frp pcg1 pcg2 hdr 0.4s (26f h ) 1.18s (78.5f h ) 0.3s (20f h ) 1.8s (120f h ) 2.1s (140f h ) 1.0s (67f h ) 2.0s (133f h ) 1.2s (80f h ) 0.55s (36f h ) 0.15s (9f h ) 3.82s (254.5f h ) 0.59s (40f h ) 12f h 1936 1956 hd horizontal direction timing chart hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll cp1, 2: lh pcgw1, 2: hh rgt: h dwn: h hpol: h slfr: h xhd: l loop counter 1976f h master clock 66.69mhz
?44 CXD2443Q mck hsync hsta hstb hck1a hck2a hck1b hck2b sh1a sh2a sh3a sh4a sh5a sh6a sh7a sh1b sh2b sh3b sh4b sh5b 340 60 20 320 300 280 260 240 220 200 180 160 140 120 100 80 40 0 1956 1936 1916 even line 0.59s (40f h ) 6f h 3.82s (254.5f h ) 3.86s (257.5f h ) 12f h 12f h sh6b sh7b hd horizontal direction timing chart (b outputs) hp1, 2, 3, 4, 5, 6, 7, 8: lllllllh slsh1, 2, 3, 4: llll rgt: h dwn: h hpol: h slfr: h sl3b: l xhd: l loop counter 1976f h master clock 66.69mhz
?45 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 520 510 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. double-speed hsync input 123456789101112 display start 21h 483 485 484 ntsc (double-speed hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h snsl: h nt-pl: h xhd: h
?46 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 520 510 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. odd field (standard hsync input) 123456789101112 display start 21h 483 485 484 ntsc (standard hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h snsl: l nt-pl: h xhd: h
?47 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 520 510 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. even field (standard hsync input) 123456789101112 display start 21h 483 485 484 ntsc (standard hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h snsl: l nt-pl: h xhd: h
?48 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 620 610 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. double-speed hsync input 123456789101112 25h 598 599 600 display start pal (double-speed hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h snsl: h nt-pl: l xhd: h
?49 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 620 610 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. odd field (standard hsync input) 123456789101112 25h 598 599 600 display start pal (standard hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h snsl: l nt-pl: l xhd: h
?50 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 620 610 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. even field (standard hsync input) 123456789101112 25h 598 599 600 display start pal (standard hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h snsl: l nt-pl: l xhd: h
?51 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 620 610 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. odd field (standard hsync input) 1 2 3 4 5 6 7 8 9 10 1112 25h 598 599 600 display start pal (pulse eliminate display, standard hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: l sl3b: l vpol: h snsl: l nt-pl: l xhd: h
?52 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 620 610 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. even field (standard hsync input) 123456789101112 25h 598 599 600 display start pal (pulse eliminate display, standard hsync input) vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: l sl3b: l vpol: h snsl: l nt-pl: l xhd: h
?53 CXD2443Q vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 70 0 60 50 40 30 20 10 1120 1110 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. odd field 45h 1033 1035 1034 1 2 3 4 5 6 7 8 9 10 1112 13 1415 16 1718 19 20 21 22 2324 25 26 2728 display start hd vertical direction timing chart vp1, 2, 3, 4: lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h xhd: l
?54 CXD2443Q 633 563 623 613 603 593 583 573 vd hsync (blk) vst hdr hsta hstb enb vck frp (1h inversed) frp (1f inversed) pcg1 pcg2 fldo vwa vwb 553 note) the frp polarity is not specified for each line and field. (blk) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. even field 45h 515 517 516 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 display start hd vertical direction timing chart vp1, 2, 3, 4 : lllh vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: lllllllll vm0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, 8j, 9j: llllhllll ma: h sl3b: l vpol: h xhd: l
?55 CXD2443Q mck rck mck rck 40 30 20 10 0 10 20 30 40 40 30 20 10 0 10 20 30 40 0 10 20 30 40 010203040 wck rstw rstr wck rstw rstr hsync hsync 4.7s (68f h ) 4.7s (68f h ) 900 910 1780 1790 1800 1810 1130 1140 2230 2240 2250 2260 4.7s (83f h ) 4.7s (83f h ) line double-speed timing chart slba = l ntsc loop counter 910f h , master clock 28.6mhz pal loop counter 1135f h , master clock 35.5mhz
?56 CXD2443Q application circuit pd485505 (nec) 0.1 47 16v 0.1 47 16v +5v +13v +5v 5.1k 1m 1m 0.1 33k 1k 10k 33 25v 0.01 3.3k 50k 33k 10k 0.01 22p l d4 1000p 33 16v +5v 0.01 50k 100p +13v +5v 5.1k 1m 1m 0.1 33k 1k 10k 33 25v 0.01 3.3k 50k 33k 10k 0.01 62p 0.39 d2 1000p 47 16v 33k 1 0.1 0.1 47 16v +5v +5v 1m 1m 5.1k 33k d1 33k 0.1 +13v 33 25v 0.01 3.3k 50k 10k 0.01 sync signal serial i/f 1000p 0.68 47p +5v 1m 1m 5.1k 33k d3 33k 0.1 +13v 33 25v 0.01 3.3k 50k 10k 0.01 1000p 0.33 47p 10k 0.01 3.3 16v 50k 100p 33 16v 0.01 +5v 1k 680 off on pre 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 81 82 83 84 88 87 86 85 89 90 99 98 97 96 95 94 92 93 xclr vwb v dd v ss tc1 peo1 pwm1 rpd1 cko1 cki1 test2 hsync vsync v ss sctr sclk sdat pre test11 fldo test1 test3 test4 test5 test6 test7 fpd1 v dd v ss vwa peo4 v ss v dd fpd4 rpd4 cki4 cko4 rstw wck rstr rck test10 sh7b sh6b sh5b v ss sh4b sh3b sh2b sh1b test9 sh7a sh6a sh5a sh4a sh3a v ss v dd sh2a sh1a xfrp frp xclp2 xclp1 pcg2 xrgt rgt hsta hstb hck1b v ss hck2b hck1a hck2a enb vck vst test8 dwn pcg1 cko2 pwm4 tc4 tc2 fpd2 peo2 pwm2 rpd2 cki2 v ss cko3 cki3 rpd3 peo3 pwm3 fpd3 tc3 cksl cki5 hdr 0.1 0.1 fpd1 rpd1 10k 0.01 3.3 16v rpd4 fpd4 3.3 16v 0.01 rpd2 fpd2 3.3 16v 0.01 50k 100p 33 16v 0.01 +5v 50k 100p 33 16v 0.01 fpd3 rpd3 l : ntsc 1.8h pal 1.2h +5v 91 10 0 d1, d2, d3, d4 : 1t363a (sony) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?57 CXD2443Q package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g

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